To perform failure analysis and process evaluation on the silicon dioxide passivation (i.e., insulation) layer(s) used in microelectronic devices (IC chios), the ability to detect defects in the layer(s) is required. Typically, holes or thickness non-uniformity in a passivation layer can cause device failure or electrical malfunction. These defects can be a micron in size or larger and need to be detected/localized over a relatively large area. Due to the random nature of the defects, the holes in the insulation can occur any place over the metallization run (i.e., the entire etched IC film surface), which, of course, would cause a failure. Besides hole defects, a thinning/non-uniformity of the passivation/insulation layer over/under/adjacent to high field regions of the IC chip can be a potential failure site, or can substantially degrade the device's electrical performance. Accordingly, a high degree of characterization of the insulating layer is desirable for process evaluation and production monitoring. That is, the ability to accurately characterize (i.e., defect detect and thickness map) the passivation/insulating layer(s) both during and after device processing is of substantial importance to ultimate device yield and device electrical performance.